FIG. 1 shows a logic activation circuit in accordance with the prior art for activating a logic circuit which contains at least one integrated supply voltage line. The logic circuit receives logic input signals E and emits processed logic signals A on output lines. The logic activation circuit in accordance with the prior art (as illustrated in FIG. 1) activates the logic circuit by using a voltage supply switching device or a switching transistor ST to connect a virtual or switched negative supply voltage line (VVSS) to a negative supply circuit VSS. After the switching transistor ST has been switched on, the positive supply voltage VDD and the negative supply voltage VSS are applied to the logic circuit, the voltage difference between the two supply voltage potentials being 1 V, for example.
The switching transistor ST in the conventional logic activation circuit in accordance with the prior art is driven using buffer circuits which are connected in series. The buffer circuits each contain two complementary MOSFETs P, N, the gate terminals of which are connected together and are connected to the output node of the preceding buffer circuit. The first buffer circuit is driven using a selection signal SEL. The buffer circuits are supplied with the positive supply voltage VDD Buffer and with the negative supply voltage VSS Buffer.
In the example illustrated in FIG. 1, a logic high drive signal SEL gives rise to a logic high potential at the control node S or gate of the switching transistor ST. On account of the high potential at the control terminal S of the switching transistor ST, the NMOS switching transistor ST is switched on and the virtual voltage supply line VVSS is thus pulled to the negative voltage potential VSS, with the result that the logic circuit is switched on. Alternatively, the switching transistor ST is provided between the positive supply voltage VDD and a virtual positive supply voltage line VVDD of the logic circuit.
A principal drawback of the logic activation circuit in accordance with the prior art (as illustrated in FIG. 1) is that, when generating the changeover control signal at the control terminal S of the switching transistor ST, a charge Q is drawn from the supply voltage potential VDD via the PMOS transistor (which is switched on) in the last buffer circuit. This means that the supply voltage is loaded with the charge Q flowing to the control terminal S. In particular, if the logic circuit is in a mobile terminal and the logic circuit is thus supplied using a battery, this severely shortens the standby times or operating times of the mobile terminal. However, the load on the voltage supply source VDD is also disadvantageous in devices which are not mobile since, as a result of reversing the charge, energy is drawn from the voltage supply source, which leads to heating. In large scale integrated circuits, in particular, this can lead to major problems which can usually only be overcome using complex cooling devices.
In many applications, the logic circuit illustrated in FIG. 1 is switched off using the logic activation circuit in order to save energy. The conventional logic activation circuit (as illustrated in FIG. 1) uses so much energy that it is worthwhile switching off the logic circuit only for relatively long switch-off times, that is to say if the energy saved by switching off the logic circuit is higher than the energy used by the logic activation circuit. In many cases, the minimum switch-off time, as of which it is worthwhile switching off the logic circuit, is too long on account of the large amount of energy used by the logic activation circuit.
The increasing miniaturization in integrated logic circuits and the resultant increased leakage current increase the power loss and thus reduce the available operating times and increase the standby power of integrated logic circuits of this type. In high-performance applications, the proportion of leakage current in the total power loss is up to 50%. Although the proportion of leakage current is considerably smaller in mobile low-power systems, reducing the leakage current constitutes an important design task as regards a long service life of the mobile terminal.
In order to effectively reduce both subthreshold currents and gate tunnel currents in the MOSFET transistors which are connected in the logic circuit, it is expedient to use the switching transistor ST in the logic activation circuit to switch off a logic circuit block that is currently not required. The leakage current within the logic circuit does not dip immediately after the logic circuit has been switched off but rather approaches a particular residual leakage current over a particular period of time. This profile is described, to a good approximation, by an exponential decay. On the other hand, the operation of driving the logic activation circuit requires additional energy which is largely needed to charge the gate capacitance of the switching transistor ST. This gate capacitance is generally very high since the switching transistor or cut-off switch has a very wide channel width in comparison with the logic transistors provided in the logic circuit. The switching transistor is designed to have a very wide channel width in order to keep the delay degradation of the logic circuit small in the active state, said delay degradation being caused by the finitely high on-resistance of the switching transistor.
For the abovementioned reasons, it is not possible to switch off the logic circuit for any desired short interval of time. On the one hand, the maximum potential saving, that is to say the minimum residual leakage current, is established only after a certain amount of time and, on the other hand, the energy used to drive the switching transistor ST and to drive the switch-off logic unit must be compensated for before a saving in energy noticeably occurs on the outside.